The 64th JSAP Spring Meeting, 2017

Presentation information

Oral presentation

13 Semiconductors » 13.4 Si wafer processing /Si based thin film /Interconnect technology/ MEMS/ Integration technology

[17a-E206-1~14] 13.4 Si wafer processing /Si based thin film /Interconnect technology/ MEMS/ Integration technology

Fri. Mar 17, 2017 9:00 AM - 12:45 PM E206 (E206)

Kuniyuki Kakushima(Titech), Tatsuya Okada(Univ. of the Ryukyus)

12:15 PM - 12:30 PM

[17a-E206-13] Modeling of Electrical Conduction in Polycrystalline Silicon Based on Trap-Assisted Tunneling

Michiru Hogyoku1, Takashi Izumida1, Seiji Onoue1 (1.Toshiba Corporation SDS Company)

Keywords:polycrystalline silicon, trap-assisted tunneling, multi-phonon transition

We have developed a novel physical model of electrical conduction across grain boundaries in polycrystalline silicon. The electrical conduction has been formulated with the trap-assisted tunneling (TAT) mechanism based on the non-radiative multi-phonon transition theory, which has been utilized originally for the modeling of "SILC", "RTN", "MONOS", and so on. The developed model successfully reproduces experimentally found weak temperature dependence of the electron mobility in polycrystalline silicon.