Oral presentation

13 Semiconductors » 13.4 Si wafer processing /Si based thin film /Interconnect technology/ MEMS/ Integration technology

[17a-E206-1~14] 13.4 Si wafer processing /Si based thin film /Interconnect technology/ MEMS/ Integration technology

Fri. Mar 17, 2017 9:00 AM - 12:45 PM E206 (E206)

Kuniyuki Kakushima(Titech), Tatsuya Okada(Univ. of the Ryukyus)

△：Presentation by Applicant for JSAP Young Scientists Presentation Award
▲：English Presentation
▼：Both of Above
No Mark：None of Above

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9:00 AM - 9:15 AM

[17a-E206-1] [JSAP Young Scientist Award Speech] Formation of low-k nanoporous SiO₂ films by F₂-laser deposition

〇Takuya Toma¹, Akira Suwa^1,2, Daichi Taniyama¹, Daisuke Nakamura¹, Hiroshi Ikenoue^1,2 (1.Kyushu Univ., 2.Department of Gigaphoton Next GLP, Kyushu Univ.)

9:15 AM - 9:30 AM

[17a-E206-2] [JSAP Young Scientist Award Speech] Fabrication of Low Resistivity Metal/Ge Contact with Amorphous Zr-Ge-N Interlayer

〇Hayato Okamoto¹, Keisuke Yamamoto¹, Dong Wang¹, Hiroshi Nakashima² (1.IGSES, Kyushu Univ., 2.GIC, Kyushu Univ.)

9:30 AM - 9:45 AM

[17a-E206-3] Ge Peaking Fin Structure Fabricated by Anisotropic and Low Temperature Neutral Beam Oxidation

〇Shuichi Noda¹, Yao-Jen Lee², Ti-Ji Hong³, Fu-Kuo Hsueh^2,3, Yiming Li³, Seiji Samukawa^1,3 (1.Tohoku Univ., 2.NDL, Taiwan, 3.NCTU, Taiwan)

9:45 AM - 10:00 AM

▲ [17a-E206-4] Schottky diode characteristics at metal/surface-damaged Ge

〇(M1)Xuan Luo¹, Tomonori Nishimura¹, Takeaki Yajima¹, Akira Toriumi¹ (1.The Univ. of Tokyo)

10:00 AM - 10:15 AM

[17a-E206-5] Reconsideration of Fermi level pinning based on redefinition of metal work function at M/S interface

〇Tomonori Nishimura¹, Takeaki Yajima¹, Akira Toriumi¹ (1.The Univ. of Tokyo)

10:15 AM - 10:30 AM

[17a-E206-6] Control of Schottky barrier heights in W/Si junctions by inserting W-silicide films composed of W-encapsulating Si clusters

〇Naoya Okada^1,2, Noriyuki Uchida¹, Toshihiko Kanayama¹ (1.AIST, 2.JST-PRESTO)

10:30 AM - 10:45 AM

[17a-E206-7] A Study on the Ultra-low Contact Resistivity of PtHf Silicide Utilizing Dopant Segregation Process

〇Yuya Tsukamoto¹, Weiguang Zuo¹, Shun-ichiro Ohmi¹ (1.Tokyo Tech)

10:45 AM - 11:00 AM

[17a-E206-8] Influence of Residual Fluorine on Internal Stress of W Thin Films

〇Yoshinori Tokuda¹, Kazunori Harada¹, Satoshi Ishikawa¹, Shunsuke Imaizumi², So Takamoto², Satoshi Izumi² (1.Toshiba, 2.Univ. of Tokyo)

11:00 AM - 11:15 AM

[17a-E206-9] Effect of annealing on threading-dislocation densities of suputter-epitaxial Ge film on Si

〇Tomohiro Nakamura¹, Wengchang Yeh¹, Shunichi Sato² (1.Shimane Univ., 2.Ricoh Co.)

11:15 AM - 11:30 AM

[17a-E206-10] Diffusion control in sub-nanometer order using Flash Lamp Annealing

〇Hideaki Tanimura¹, Hikaru Kawarazaki¹, Kazuhiko Fuse¹, Makoto Abe¹, Takayuki Aoyama¹, Shinnichi Kato¹, Ippei Kobayashi¹ (1.SCREEN Semiconductor Solutions Co., Ltd.)

11:45 AM - 12:00 PM

△ [17a-E206-11] Solid-phase crystallization for large-grained Ge thin film on glass and demonstration of its high hole mobility

〇Ryota Yoshimine¹, Kaoru Toko¹, Takashi Suemasu¹ (1.Univ. of Tsukuba)

12:00 PM - 12:15 PM

[17a-E206-12] Inhomogeneous crystallization of sputter-deposited amorphous Ge films

〇Ryusuke Nakamura¹, Masayuki Okugawa¹, Hiroshi Numakura¹, Manabu Ishimaru², Hidehiro Yasuda³ (1.Osaka Pref. Univ., 2.Kyushu Inst. Univ., 3.Osaka Univ.)

12:15 PM - 12:30 PM

[17a-E206-13] Modeling of Electrical Conduction in Polycrystalline Silicon Based on Trap-Assisted Tunneling

〇Michiru Hogyoku¹, Takashi Izumida¹, Seiji Onoue¹ (1.Toshiba Corporation SDS Company)

12:30 PM - 12:45 PM

[17a-E206-14] Letter Recognition by Neural Network using Poly-Si Thin Film Transistor

〇Sumio Sugisaki¹, Matsuda Tokiyoshi¹, Mutsumi Kimura¹ (1.Ryukoku Univ.)

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