[20p-234B-1~17] 22.1 Joint Session M "Phonon Engineering"

△ [20p-234B-12] Heat Engineering of Planar Si-nanowire Thermoelectric Generator

〇(PC)Motohiro Tomita¹, Takehiro Kumada¹, Keisuke Shima¹, Tianzhuo Zhan¹, Hui Zhang^1,2, Takashi Matsukawa³, Takeo Matsuki^1,3, Takanobu Watanabe¹ (1.Waseda Univ., 2.Gunma Univ., 3.AIST)

Keywords:semiconductor, thermoelectric generator, heat engineering

We demonstrated both numerically and experimentally that the sub-µm class short Si-NWs lying on the SiO₂/Si-substrate of SOI wafer show high TE properties. However, the TE performance was found to be limited by the parasitic heat resistance of the SiO₂ layer and the base-substrate. Most of the heat energy is dissipated in the thick substrate and thus the temperature difference in the short Si-NWs is drastically decreased. Further enhancement of the TE performance requires the engineering of the heat resistance in the substrate. In this study, we numerically investigated the effect of the thickness of the SiO₂ insulating layer underneath Si-NWs and the base-substrate under the SiO₂ layer by FEM simulations. Suppression of the base-substrate heat resistance is effective to increase the TE power density. Moreover, the tuning of the SiO₂ insulating layer underneath the Si-NWs is also indispensable to establish a temperature difference in Si-NW for the best TE performance.