The 79th JSAP Autumn Meeting, 2018

Presentation information

Oral presentation

13 Semiconductors » 13.1 Fundamental properties, surface and interface, and simulations of Si related materials

[21p-135-1~16] 13.1 Fundamental properties, surface and interface, and simulations of Si related materials

Fri. Sep 21, 2018 1:00 PM - 5:15 PM 135 (135)

Tomo Ueno(TUAT), Koichiro Saga(Sony)

3:45 PM - 4:00 PM

[21p-135-11] Lateral etching of HfN0.5 narrow line utilizing diluted HF solution

〇(M1)Yizhe Ding1, Rengie Mark D Mailig1, Sohya Kudoh1, Shun-ichiro Ohmi1 (1.Tokyo Tech)

Keywords:wet etching, narrow line

The so-called high-κ gate dielectrics are regarded as the most promising candidates to overcome the limitations of transistor scaling, such as equivalent-oxide-thickness (EOT) and gate length (Lg) scaling. We have reported that 0.5 nm EOT utilizing bilayer HfNx gate insulators with in-situ formed HfN0.5 gate electrode. In this paper, the lateral etching of HfN0.5 gate electrode utilizing diluted HF (DHF) solution was investigated. The lateral etching rate of 1.1 µm/min was confirmed by 4 µm L/S pattern. Moreover, the precise control of lateral etching for HfN0.5 gate electrode was realized which would be suitable for narrow gate formation.