The 79th JSAP Autumn Meeting, 2018

Presentation information

Oral presentation

4 JSAP-OSA Joint Symposia 2018 » 4.2 Photonics Devices, Photonic Integrated Circuit and Silicon Phonics

[21p-211B-1~9] 4.2 Photonics Devices, Photonic Integrated Circuit and Silicon Phonics

Fri. Sep 21, 2018 1:15 PM - 4:15 PM 211B (211-2)

Yasutomo Ota(Univ. of Tokyo), Nobuhiko Nishiyama(Tokyo Tech)

1:15 PM - 1:45 PM

[21p-211B-1] [INVITED] Ultralow Latency Computation based on Integrated Nanophotonics

Masaya Notomi1,2, Kengo Nozaki1,2, Shota Kita1,2, Akihiko Shinya1,2, Tohru Ishihara3, Koji Inoue4 (1.NTT Basic Research Labs., 2.NTT Nanophotonics Center, 3.Kyoto Univ., 4.Kyushu Univ.)

Keywords:nanophotonics, optical computing

Moore’s law for CMOS computers is still continuing, but its near-future saturation is now being discussed. One of the serious saturations is about its latency. The computation delay for a CMOS transistor is already saturated above 10 ps, which will be problematic when ultralow-latency response is required for broad-band data streams, even with parallelization or pipe-line processing. We regard that optical circuits may serve as ultralow-latency computation circuits if they are small enough and tightly combined with electronic circuits. The former requires nanophotonic devices/circuits and the former requires OE/EO conversion with ultrasmall capacitance. In this talk, first, we present our recent achievement in ultrasmall-capacitance OE/EO conversions. Then, we show that if we adopt a certain type of logic (optical pass-gate logic), ultralow-latency computation will be possible using nanophotonic circuits. We show several examples including optical full-adders consisting of electro-optic switches and digital-to-analogue converters, Boolean logic circuits based on linear optic elements, verctor-matrix multiplication for neuromorphic computing.