[18a-B11-1~11] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

[18a-B11-10] Power-gating performance of SRAM using various retention techniques

〇Takumi Hara¹, Hayato Yoshida¹, Daiki Kitagata¹, Shuu'ichirou Yamamoto¹, Satoshi Sugahara¹ (1.Tokyo Tech)

Keywords:Power-gating, SRAM, Ultra-low static power