[18a-B11-1~11] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

[18a-B11-9] Performance evaluation of power gating architectures using nonvolatile/virtually-nonvolatile Flip-Flops

〇Kenichiro Takiguchi¹, Daiki Kitagata¹, Tsubasa Matsuzaki¹, Syuu'ichirou Yamamoto¹, Satoshi Sugahara¹ (1.FIRST, Tokyo Inst. of Tech.)

Keywords:power gating, Flip-Flop