[18a-B11-1~11] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

[18a-B11-5] Statistical Analyses of Worst Case SRAM Data Retention Voltage by Extreme Value Theory

〇Tomoko Mizutani¹, Kiyoshi Takeuchi¹, Takuya Saraya¹, Masaharu Kobayashi^1,2, Toshiro Hiramoto¹ (1.IIS, Univ. of Tokyo, 2.VDEC, Univ. of Tokyo)

Keywords:SRAM, data retention voltage, extreme value theory

It is well known that the lowest operation voltage of scaled SRAM arrays is governed by random variability and is determined by the worst case cell. Therefore, estimating the worst case value is important. The worst case value can be estimated by measuring the operation voltage of all the cells, and determining the statistical distribution that the measured values follow. However, in production, measurements of all the individual cells are not realistic. In this study, the behavior of the worst case data retention voltage (DRV) in SRAM cells was statistically analyzed using the extreme value theory.