[18p-B11-1~14] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

△ [18p-B11-7] Effect of thermal annealing on InAs-On-Insulator substrates fabricated by Smart Cut

〇Kei Sumita¹, Jun Takeyasu¹, Kimihiko Kato¹, Kasidit Toprasertpong¹, Mitsuru Takenaka¹, Shinichi Takagi¹ (1.The Univ. of Tokyo)

Keywords:III-V semiconductor, MOSFET, Smart Cut

III-V nMOSFETs are expected for 3D CMOS because the reduction in the process temperature can be easily realized. We report that physical properties of InAs-OI fabricated by the Smart Cut method were evaluated and annealing at 400ºC is significantly effective to recover the crystallinity of InAs-OI. InAs-OI substrates fabricated by the Smart Cut method were annealed at each temperature of 200-400ºC and crystallinity and electron mobility are compared by Raman spectra and Hall measurement. Finally, 20-nm-thick InAs-OI nMOSFET, which was planarized for RMS of 0.3 nm by CMP, was demonstrated.