[19p-E304-1~13] 13.4 Si系プロセス・Si系薄膜・MEMS・装置技術

▲ [19p-E304-2] Variance reduction during the fabrication of 1x-nm-diameter Si pillar arrays

〇ShuJun YE¹、Kikuo YAMABE¹、Tetsuo ENDOH¹ (1.Tohoku Univ.)

キーワード：Variance reduction, Si nanopillar, self-limiting oxidation

We recently fabricated uniform 1x-nm-diameter Si pillar arrays with a reduced diameter variance (to +/-0.5 nm) and a cylindrical shape, which could be used for the fabrication of the vertical gate-all-around MOSFETs. In this work, we experimentally and theoretically explain how self-limiting oxidation reduces the diameter variance both at the height direction of Si pillar and among nanopillar arrays.