The 66th JSAP Spring Meeting, 2019

Presentation information

Symposium (Oral)

Symposium » Nanoscale 2D/3D analyses for new device and materials development II

[10p-W933-1~9] Nanoscale 2D/3D analyses for new device and materials development II

Sun. Mar 10, 2019 1:30 PM - 5:45 PM W933 (W933)

Yuji Matsumoto(Tohoku Univ.), Takashi Furukawa(Hitachi High-Technologies Corporation)

1:30 PM - 2:00 PM

[10p-W933-1] Necessity of 2D/3D nano measurements from the viewpoint of semiconductor devices

Koji Usuda1 (1.Toshiba Memory)

Keywords:semiconductor, device, three-dimensional structure

Si semiconductor device technologies have continued to develop for more than 30 years based on the so-called "scaling law. However, in the past 10 years, technology development based on the conventional roadmap for the Si devices is approaching its limit, “reaching the end of the Si-LSI roadmap". To overcome this problem and achieve further development, the latest research and development is focusing on new device technologies that do not rely on miniaturization. One of a representative is three-dimensionalization of planar type devices. Typical examples are change to a three-dimensional structure of a 2D transistor channel, and realization of a three-dimensional memory device incorporating a stacking technology. Then, in this presentation, we introduce the latest trend of Si based semiconductor devices and discuss some of expectations for nanoscale analysis technology supporting device development.