[11a-Z09-1~12] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

[11a-Z09-10] Design and analysis of 8kB SRAM macro using a new ultralow-voltage-retention architecture

〇Yusaku Shiotsu¹, Daiki Kitagata¹, Shuu'ichirou Yamamoto¹, Satoshi Sugahara¹ (1.FIRST, Tokyo Inst. of Tech.)

Keywords:Powergating, SRAM, Low static power