[11a-Z09-1~12] 13.5 デバイス／配線／集積化技術

▲ [11a-Z09-3] GAA p-type poly-Si junctionless nanowire transistor with ideal subthreshold slope

〇(D)Minju Ahn¹、Takuya Saraya¹、Masaharu Kobayashi¹、Toshiro Hiramoto¹ (1.Institute of Industrial Science, The University of Tokyo)

キーワード：Gate-all-around nanowire structure, Poly-Si junctionless transistor, Ideal subthreshold slope

In this work, we fabricated the gate-all-around (GAA) p-type poly-Si junctionless (JL) nanowire (NW) transistors, and observed excellent subthreshold characteristics close to ideal subthreshold slope (60mV/dec.) as well as high on/off current ratio (~1.2x10⁸) and low off-current (<10^-13A) thanks to improved fabrication processes as well as highly suppressed grain boundary defects. The origins will be discussed based on experimental results.