[9a-Z10-1~11] 13.4 Si系プロセス・Si系薄膜・MEMS・装置技術

▲ [9a-Z10-6] Consideration of relationship between the variation of Gate Oxide Thicknesses and the
density of interface states for MOS structure

〇Mickael Lozach¹、Sommawan Khumpuang^1,2、Shiro Hara^1,2 (1.AIST, Device Technology Research Institute, Minimal System Group, Tsukuba、2.Minimal Fab Promoting Organization, AIST, Tsukuba)

キーワード：interface state density, gate oxide, MOS

P-channel metal-oxide-semiconductor field effect transistors (p-MOSFET), also called pMOS, are fabricated by an advanced semiconductor fab: Minimal Fab. Minimal Fab is characterized by a modern, cost effective, fabrication concept with minimized silicon wafers (12.5 mm) encapsulated in a shuttle to avoid any contamination keeping white room condition during the full fabrication process, without the space and budget of a mega fab. Here, the density of interface state (D_it) is monitored as a function of the oxide gate thickness (T_ox) to improve the yield of pMOS devices. The coupled D_it - T_ox variable can improve the reliability of pMOS characterization by underlining the interface Si-SiO₂ quality, which is associated to electrical performance by D_it. Prior to the gate oxide deposition, different RCA chemical cleaning are realized in three different Minimal Fab stations, then, pMOS devices performances are compared and discussed in terms of D_it. An excellent interface quality is obtained with D_it < 5×10¹⁰ eV^-1 cm^-2.