The 67th JSAP Spring Meeting 2020

Presentation information

Oral presentation

13 Semiconductors » 13.5 Semiconductor devices/ Interconnect/ Integration technologies

[12p-A305-1~13] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

Thu. Mar 12, 2020 1:45 PM - 5:15 PM A305 (6-305)

Munehiro Tada(NEC), Marina Yamaguchi(Kioxia)

4:45 PM - 5:00 PM

[12p-A305-12] Development of Via-Switch with Multi-Layered a-Si/SiN/a-Si Varistor

Noriyuki Iguchi1, Naoki Banno1, Koichiro Okamoto1, Hideaki Numata1, Masanori Hashimoto2, Tadahiko Sugibayashi1, Toshitsugu Sakamoto1, Munehiro Tada1 (1.NEC Corp., 2.Oosaka Univ.)

Keywords:Atom switch, FPGA, Selector

Two-varistors selected complementary atom switch (a.k.a. via-switch) is newly proposed for a nonvolatile, highly-dense and low-power FPGA. A compact via-switch is placed at each cross-point, in which the two control lines connected to the varistors can realize the multiple fan-outs (FOs) without select transistors. In this work, a newly a-Si/SiN/a-Si varistor with a novel triple layered SiN shows superior nonlinearity (NL) of 1.1x105 with maximum current density of 1.63MA/cm2. Since we discuss the conducting mechanism of the proposed varistor to improve the NL performance, the effects of composition of the SiN layer are analyzed. We clarify that the improved NL of the a-Si/SiN/a-Si varistor is caused by its staircase barrier height. The via-switch is a strong candidate for switch elements of low-power FPGA.