The 67th JSAP Spring Meeting 2020

Presentation information

Oral presentation

13 Semiconductors » 13.4 Si processing /Si based thin film / MEMS / Equipment technology

[14p-A305-1~14] 13.4 Si processing /Si based thin film / MEMS / Equipment technology

Sat. Mar 14, 2020 1:45 PM - 5:30 PM A305 (6-305)

Hiroshi Ikenoue(Kyushu Univ.), Masato Sone(Tokyo Tech)

2:00 PM - 2:15 PM

[14p-A305-2] The low temperature fabrication of gate-first Schottky barrier pMOSFET with PdErSi source and drain

RengieMark Domincel Mailig1, Yuichiro Aruga1, Min Gee Kim1, Shun-ichiro Ohmi1 (1.Tokyo Tech)

Keywords:PdErSi, SB MOSFET, gate-first process

The main requirement for the integration of the high-k gate insulators such as HfN or HfO2 in the gate-first CMOS fabrication is the low-thermal budget process below 500°C. In this work, the PdErSi as S/D material in the gate-first SB p- channel MOSFET (pMOSFET) was investigated.