The 67th JSAP Spring Meeting 2020

Presentation information

Oral presentation

13 Semiconductors » 13.3 Insulator technology

[15a-A305-1~13] 13.3 Insulator technology

Sun. Mar 15, 2020 9:00 AM - 12:30 PM A305 (6-305)

Takanobu Watanabe(Waseda Univ.), Koji Kita(Univ. of Tokyo)

11:45 AM - 12:00 PM

[15a-A305-11] Proposal of a measurement method to discriminate different types of traps in n-Ge MOS gate nsulators

Mengnan Ke1, Mitsuru Takenaka1, Shinichi Takagi1 (1.Univ. Tokyo)

Keywords:Ge, MOS interfaces

To improve the reliability of Ge gate stacks, understanding of slow trap characteristics in Ge MOS interfaces is extremely important. We have applied the conventional method to estimate Nst in n-Ge MOS interfaces. Here, hysteresis observed in the C-V scan with low Vstop (Eox) is attributed to electron trapping into existing slow trap sites. In this study, we propose a new measurement scheme to discriminate pre-existing, generated electron slow traps and hole traps under electrical stress and apply this method to Al2O3/GeOx/n-Ge with PPO MOS interfaces. It is found that, when higher Vstop (Eox) is applied, both hole trapping and generation of new electron slow traps occur.