The 67th JSAP Spring Meeting 2020

Presentation information

Oral presentation

13 Semiconductors » 13.3 Insulator technology

[15a-A305-1~13] 13.3 Insulator technology

Sun. Mar 15, 2020 9:00 AM - 12:30 PM A305 (6-305)

Takanobu Watanabe(Waseda Univ.), Koji Kita(Univ. of Tokyo)

12:00 PM - 12:15 PM

[15a-A305-12] Comparison of carrier trap characteristics in different interfacial layers of n-Ge MOS structures

Mengnan Ke1, Mitsuru Takenaka1, Shinichi Takagi1 (1.Univ. Tokyo)

Keywords:Ge, MOS interfaces

One of the key technologies for realizing Ge CMOS is the formation of gate stacks with low defect densities. (HfO2)/Al2O3/GeOx/Ge interfaces realized by post plasma oxidation (post-PO) are promising for reducing interface states density. However, a remaining critical issue is the existence of a large amount of slow traps, which can be an inherent problem for Ge gate stacks. It has been reported that Y-doped GeOx interfaces and Al2O3/GeOx/Ge formed by pre plasma oxidation (pre-PO) can reduce slow trap density (Nst). However, reduction in Nst is not sufficient yet, particularly for electrons. Thus, understanding of physical origins of the slow electron traps and the carrier trapping properties is strongly required to establish a guideline for further reduction in Nst and a method of the oxide reliability prediction for Ge MOS interfaces. We have proposed a new measurement to discriminate existing and generated electron slow traps. It has been found that only existing slow traps are responsible in low Eox, while generation of slow traps and hole trapping additionally occur in high Eox. In this study, we compare the existing electron, generated electron and hole trap density of n-Ge MOS interfaces with different interfacial layers including Y2O3 under electrical stress by utilizing the above technique.