[15a-A305-1~13] 13.3 絶縁膜技術

▲ [15a-A305-11] Proposal of a measurement method to discriminate different types of traps in n-Ge MOS gate nsulators

〇Mengnan Ke¹、Mitsuru Takenaka¹、Shinichi Takagi¹ (1.Univ. Tokyo)

キーワード：Ge, MOS interfaces

To improve the reliability of Ge gate stacks, understanding of slow trap characteristics in Ge MOS interfaces is extremely important. We have applied the conventional method to estimate N_st in n-Ge MOS interfaces. Here, hysteresis observed in the C-V scan with low V_stop (E_ox) is attributed to electron trapping into existing slow trap sites. In this study, we propose a new measurement scheme to discriminate pre-existing, generated electron slow traps and hole traps under electrical stress and apply this method to Al₂O₃/GeO_x/n-Ge with PPO MOS interfaces. It is found that, when higher V_stop (E_ox) is applied, both hole trapping and generation of new electron slow traps occur.