[23a-P10-1~14] 13.7 Compound and power devices, process technology and characterization

[23a-P10-11] Calculation of interface trap level at GaN/SiO₂ interface

〇Hidenori Tsuji¹, Yuki Ohuchi¹, Katsunori Ueno¹, Shinya Takashima¹, Ryo Tanaka¹, Masaharu Edo¹ (1.Fuji Electric)

Keywords:semiconductor, GaN, MOS interface

In order to investigate the origin of the interface state of the p-type GaN/SiO₂ interface, we calculated the band structure for the Ga polar plane GaN/SiO₂ structure using first-principles calculation. As a result, it was found that a localized level derived from the interface is formed in the gap near the valence band, which may result in a whole trap. Furthermore, it was suggested that the introduction of defects at the interface could change the energy of this localized level, making it difficult for trapped holes to be released.