[24a-E103-1~13] 13.4 Si processing /Si based thin film / MEMS / Equipment technology

[24a-E103-1] Investigation and Countermeasure of Abnormal Increase in Parasitic resistance of Linear Region of SOI NMOS of Minimal Fab

〇Takeshi Hamamoto¹, Kazushige Sato², Sommawan Khumpuang², Shiro Hara² (1.MINIMAL, 2.AIST)

Keywords:SOI, MOSFET

Minimal fab is a production system targeting high-mix low-volume production. We are now focusing on creating a PDK (Process Design Kit) and improving the operating accuracy of MOSFETs and enlargining the process robustness in order to support circuit operations based on a wide range of user designs. At the stage of advancing this practical structure and its development from the principle prototype level, it is necessary to reduce the parasitic resistance of the transistor to a level where there is no problem in terms of transistor characteristics. This paper describes the analysis and reduction method of parasitic resistance.