[16a-E302-1~6] 【Open Symposium】Connection : From BEOL to Tiplet, and to the Future **In corporation with The Japan Institute of Electronics
Packaging (JIEP)

[16a-E302-3] NRE Cost Reduction of Domain Specific Accelerators by a Multi-IP SoC

〇Shinichi Ouchi¹ (1.AIST)

Keywords:Domain Specific Accelerator, Proof of Concept, NRE Cost

Domain specific accelerators (DSAs) have become one of the most effective solutions in the aspect of the power performance. However, its development cost is very expensive because the DSA is a custom SoC. AI Chip design center (AIDC), a joint project of AIST and University of Tokyo, is developing a multi-IP SoC (System on a Chip) framework as a method to reduce non recursing cost on developing a DSA. In this presentation, the project is reviewed and its extension to business in practice is discussed.