[16p-A403-1~20] 13.5 デバイス／配線／集積化技術

▲ [16p-A403-18] Effects of Annealing on Thermal Boundary Resistance of Low-k Interlayer Dielectrics

〇Mao Xu¹、Zhi Cao²、Akitoshi Okino¹、Tianzhuo Zhan³ (1.FIRST, Tokyo Tech、2.Waseda Univ.、3.Toyo Univ.)

キーワード：thermal boundary resistance, interlayer dielectric, low-k

Thermal boundary resistance (TBR) between the metal and the interlayer dielectric in interconnect structures is considered to play an important role in the temperature rise in logic semiconductors. Therefore, investigation and improvement of the thermal properties in the boundary formed by interconnected metals and dielectrics are crucial for thermal management in logic semiconductor devices. In this study, films (Cu/Ta/TaN/SOG/Si-substrate) in stacking structure simulating interconnects were fabricated to evaluate their thermal properties including TBR and thermal resistance in logic semiconductors by FDTR. In addition, interlayer analysis using FT-IR was also carried out.