[G-10] Advanced CMOS: Device, Process and Material

[G-10-02] Impact of Back-side Power Delivery Network Layout on the FinFET Device Performance

Goutham Arutchelvan¹, Thomas Chiarella¹, Hiroaki Arimura¹, Anabela Veloso¹, Anne Jourdain¹, Eugenio Dentoni Litta¹, Naoto Horiguchi¹, 〇Jerome Mitard¹ (1. imec (Belgium))

Presentation style: On-site (in-person)

https://doi.org/10.7567/SSDM.2022.G-10-02

Backside power delivery (BSPDN) with Buried Power Rail (BPR) is an essential enabler for CMOS scaling beyond the 5nm node. In this work, we show that integrating BPR and Nano-Through Silicon Via (n-TSV) close to the active channel does not degrade the device performance, thus, confirming that the stress transfer from BSPDN elements is rather weak. Design guidelines with respect to n-TSV proximity and number of VBPR vias for optimized device performance and reduced footprint is discussed.