3:00 PM - 3:15 PM
[G-6-07 (Late News)] Modeling and Simulation of Antiferroelectric FETs with Oxide Semiconductor Channel Using Half-Loop Hysteresis for Memory Applications
Presentation style: On-site (in-person)
https://doi.org/10.7567/SSDM.2022.G-6-07
Abstract password authentication.
Password to download abstracts has been informed in the confirmation mail.