[J-10] DRAM, SRAM, and 3D NAND

[J-10-04] A Loadless 4T SRAM Cell Powered by Gate Leakage Current and Tolerant of Random Dopant Fluctuation and Surface Roughness at Si-SiO₂ Interface

〇Yihan Zhu¹, Takashi Ohsawa¹ (1. Waseda Univ. (Japan))

Presentation style: On-site (in-person)

https://doi.org/10.7567/SSDM.2022.J-10-04

Monte Carlo simulations under Vth fluctuation and gate leakage current variation due to random dopant fluctuation (RDF) and surface roughness at Si-SiO2 interface are conducted for a new loadless 4T SRAM cell in 32nm whose data is held by gate leakage current of the access PFETs with EOTp less than EOPn. Read and write SNMs are shown larger than 6TSRAM. Though the hold SNM is smaller than 6TSRAM, its -5 sigma value is extrapolated to 60mV at VDD=1V and T=25 deg. C