[A-4-1] Drain Disturb Relaxation by Substrate bias Selecting Scheme for Sector Erase Flash Memory with Conventional Single Stacked Gate Cell Structure

M. Yoshimi、N. Shinmura、T. Tanigami、K. Hakozaki、S. Sato、K. Iguchi (1.VLSI Development Laboratories, IC Tenri Group, SHARP Corporation)

https://doi.org/10.7567/SSDM.1997.A-4-1