Evaluation of 0.3 μm Poly-Silicon CMOS Circuits for Intelligent Power IC Application

Tomoko Matsudai; Mamoru Terauchi; Makoto Yoshimi; Norio Yasuhara; Yukihiro Ushiku; Akio Nakagawa

doi:https://doi.org/10.7567/SSDM.1997.C-10-2

1997 International Conference on Solid State Devices and Materials

1997年9月16日〜 1997年9月19日
ACT CITY Hamamatsu, Hamamatsu, Japan

[C-10-2] Evaluation of 0.3 μm Poly-Silicon CMOS Circuits for Intelligent Power IC Application

Tomoko Matsudai、Mamoru Terauchi、Makoto Yoshimi、Norio Yasuhara、Yukihiro Ushiku、Akio Nakagawa (1.Advanced Semiconductor Devices Research Laboratories, Toshiba Corporation)

https://doi.org/10.7567/SSDM.1997.C-10-2

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