[D-10-3] Novel Gate-Recess Process for the Reduction of Parasitic Phenomena Due to Side-Etching in InAlAs/InGaAs HEMTs

Tetsuya Suemitsu、Takatomo Enoki、Haruki Yokoyama、Yasunobu Ishii (1.NTT System Electronics Laboratories)

https://doi.org/10.7567/SSDM.1997.D-10-3