Enhancement-Mode In<sub>0.53</sub>Ga<sub>0.47</sub>As n-MOSFET with Self-aligned Gate-first Process and CVD HfAlO Gate Dielectric

J. Lin; S. J. Lee; H. J. Oh; G. K. Dalapati; D. Z. Chi; G. Q. Lo; D. L. Kwong

doi:https://doi.org/10.7567/SSDM.2008.B-1-2

2008 International Conference on Solid State Devices and Materials

2008年9月23日〜 2008年9月26日
Tsukuba International Congress Center (EPOCHAL TSUKUBA), Ibaraki, Japan

[B-1-2] Enhancement-Mode In_0.53Ga_0.47As n-MOSFET with Self-aligned Gate-first Process and CVD HfAlO Gate Dielectric

J. Lin¹、S. J. Lee¹、H. J. Oh¹、G. K. Dalapati²、D. Z. Chi²、G. Q. Lo³、D. L. Kwong³ (1.National Univ. of Singapore、2.Inst. of Materials Res. and Eng.、3.Inst. of Microelectronics, Singapore)

https://doi.org/10.7567/SSDM.2008.B-1-2

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2008 International Conference on Solid State Devices and Materials

[B-1-2] Enhancement-Mode In0.53Ga0.47As n-MOSFET with Self-aligned Gate-first Process and CVD HfAlO Gate Dielectric

[B-1-2] Enhancement-Mode In_0.53Ga_0.47As n-MOSFET with Self-aligned Gate-first Process and CVD HfAlO Gate Dielectric