Design and Optimization of Gate Sidewall Spacers to Achieve 45nm Ground Rule for High-performance Applications

T. Miyashita; K. Ookoshi; A. Hatada; K. Ikeda; Y. S. Kim; M. Nishikawa; T. Sakoda; K. Hosaka; H. Kurata

doi:https://doi.org/10.7567/SSDM.2008.B-5-1

2008 International Conference on Solid State Devices and Materials

2008年9月23日〜 2008年9月26日
Tsukuba International Congress Center (EPOCHAL TSUKUBA), Ibaraki, Japan

[B-5-1] Design and Optimization of Gate Sidewall Spacers to Achieve 45nm Ground Rule for High-performance Applications

T. Miyashita¹、K. Ookoshi²、A. Hatada²、K. Ikeda¹、Y. S. Kim¹、M. Nishikawa²、T. Sakoda¹、K. Hosaka¹、H. Kurata¹ (1.Fujitsu Labs. Ltd.、2.Fujitsu Microelectronics Ltd., Japan)

https://doi.org/10.7567/SSDM.2008.B-5-1

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