Copper Plug Barrier Process Optimization for Reliable Transistor Performance

S. K. Manhas; M. Chen; K. D. Buddharaju; H. Y. Li; R. Murthy; S. Balakumar; N. Singh; G. Q. Lo; D. L. Kwong

doi:https://doi.org/10.7567/SSDM.2008.P-2-8

2008 International Conference on Solid State Devices and Materials

Sep 23, 2008 - Sep 26, 2008
Tsukuba International Congress Center (EPOCHAL TSUKUBA), Ibaraki, Japan

[P-2-8] Copper Plug Barrier Process Optimization for Reliable Transistor Performance

S. K. Manhas¹, M. Chen¹, K. D. Buddharaju¹, H. Y. Li¹, R. Murthy¹, S. Balakumar¹, N. Singh¹, G. Q. Lo¹, D. L. Kwong¹ (1.Inst. of Microelectronics, Singapore)

https://doi.org/10.7567/SSDM.2008.P-2-8

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