[B-2-4] New Criteria for Suppressing Extrinsic Defect Generation in Ultra Thin SiON Gate Insulator (EOT<1.4nm) for Advanced CMOSFETs

S. Shimamoto¹、H. Kawashima²、T. Kikuchi¹、Y. Yamaguchi²、A. Hiraiwa² (1.Hitachi, Ltd.(Japan)、2.Renesas Tech. Corp.(Japan))

https://doi.org/10.7567/SSDM.2009.B-2-4