[C-1-6] Bitline-Capacitance-Insensitive Readout Circuit using Capacitive-Feedback Charge-Integration Scheme for Low-Voltage FeRAM

K. Kotani¹、Y. Koshimoto¹、T. Ito¹ (1.Tohoku Univ.)

https://doi.org/10.7567/SSDM.2009.C-1-6