[D-7-2] Substrate Noise Analysis of Digital Circuits to Optimize Substrate-Contact Space

S. Komatsu¹、M. Yamaoka¹、Y. Kanno¹、Y. Yasu²、K. Ishibashi²、K. Osada¹ (1.Hitachi, Ltd.(Japan)、2.Renesas Tech. Corp.(Japan))

https://doi.org/10.7567/SSDM.2009.D-7-2