Substrate Noise Analysis of Digital Circuits to Optimize Substrate-Contact Space

2009 International Conference on Solid State Devices and Materials

Oct 6, 2009 - Oct 9, 2009
Sendai Kokusai Hotel, Miyagi, Japan

S. Komatsu¹, M. Yamaoka¹, Y. Kanno¹, Y. Yasu², K. Ishibashi², K. Osada¹ (1.Hitachi, Ltd.(Japan), 2.Renesas Tech. Corp.(Japan))