[D-7-3] Within-Die/Wafer Variation Analysis of Basic CMOS Circuits based on Surface-Potential-Model HiSIM2

K. Johguchi¹, A. Kaya¹, S. Izumi¹, H. J. Mattausch¹, T. Koide¹, N. Sadachika¹ (1.Hiroshima Univ.)

https://doi.org/10.7567/SSDM.2009.D-7-3