[G-4-2] The Operation Scheme and Process Optimization in TLC(Triple Level Cell) NAND Flash Characteristics

J. Yang¹、M. Park¹、S. Jung¹、S. Park¹、S. Cho¹、J. An¹、J. Lee¹、H. Lee¹、M. K. Cho¹、K. O. Ahn¹、K. Jin¹、Y. Koh¹ (1.Hynix Semiconductor Inc.)

https://doi.org/10.7567/SSDM.2009.G-4-2