Reducing the Gate Charge of Dual Gate Power VDMOSFET by Pseudo-Gate

C. N. Liao; F. T. Chien; C. M. Lin; C. H. Ho; Y. T. Tsai

doi:https://doi.org/10.7567/SSDM.2009.P-14-1

2009 International Conference on Solid State Devices and Materials

2009年10月6日〜 2009年10月9日
Sendai Kokusai Hotel, Miyagi, Japan

[P-14-1] Reducing the Gate Charge of Dual Gate Power VDMOSFET by Pseudo-Gate

C. N. Liao¹、F. T. Chien²、C. M. Lin³、C. H. Ho¹、Y. T. Tsai¹ (1.National Central Univ.(Taiwan)、2.Feng Chia Univ.(Taiwan)、3.Southern Taiwan Univ.(Taiwan))

https://doi.org/10.7567/SSDM.2009.P-14-1

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