[P-2-12] Evaluation of Thin LSI Wafers by Capacitance-Time (C-t) Measurement for the Process Characterization of Three-Dimensional (3D) Integration
J.C. Bea1, M. Murugesan1, Y. Ohara1, A. Noriki1, H. Kino1, K. W. Lee1, T. Fukushima1, T. Tanaka1, M. Koyanagi1
(1.Tohoku Univ.)
https://doi.org/10.7567/SSDM.2009.P-2-12