Rigorous Design of 20 nm Level SOI 4-T FinFETs for Low Standby Power by Extracting Parameters from the Pre-stage 50 nm Technology Node Devices

S. Cho; S. W. Kim; K. Endo; S. O'uchi; T. Matsukawa; Y. Son; J. P. Kim; K. Sakamoto; Y. Liu; B. G. Park; M. Masahara

doi:https://doi.org/10.7567/SSDM.2009.P-3-2

[P-3-2] Rigorous Design of 20 nm Level SOI 4-T FinFETs for Low Standby Power by Extracting Parameters from the Pre-stage 50 nm Technology Node Devices

S. Cho¹, S. W. Kim¹, K. Endo², S. O'uchi², T. Matsukawa², Y. Son¹, J. P. Kim¹, K. Sakamoto², Y. Liu², B. G. Park¹, M. Masahara² (1.Seoul National Univ.(Korea), 2.AIST(Japan))

https://doi.org/10.7567/SSDM.2009.P-3-2

2009 International Conference on Solid State Devices and Materials

[P-3-2] Rigorous Design of 20 nm Level SOI 4-T FinFETs for Low Standby Power by Extracting Parameters from the Pre-stage 50 nm Technology Node Devices