[P-3-4] Investigation of Novel Si/SiGe Hetero Structures and Gate Induced Source Tunneling for Improvement of P-channel Tunnel FETs

H. G. Virani¹, R. B. Rao¹, A. Kottantharayil¹ (1.Indian Inst. Of Tech. Bombay)

https://doi.org/10.7567/SSDM.2009.P-3-4