[P-5-5] 4 ch x 10 Gb/s Parallel Phase-synchronization Architecture and a Phase-adjuster Circuit using a Common Clock Signal

H. Katsurai¹、J. Terada¹、Y. Ohtomo¹ (1.NTT Microsystem Integration Labs.)

https://doi.org/10.7567/SSDM.2009.P-5-5