High-k/Ge Gate Stack with an EOT of 0.56 nm by Controlling High-k/Ge Interface Reaction Using Ultrathin AlO<sub>x</sub> Interlayer

Ryohei Tanaka

Presentation information

Oral presentation

13. Semiconductors A (Silicon) » 13.3 Insulator technology

[17p-B5-1~21] 13.3 Insulator technology

Tue. Sep 17, 2013 1:00 PM - 6:30 PM B5 (TC2 2F-201)

5:15 PM - 5:30 PM

△ [17p-B5-17] High-k/Ge Gate Stack with an EOT of 0.56 nm by Controlling High-k/Ge Interface Reaction Using Ultrathin AlO_x Interlayer

^○Ryohei Tanaka¹, Iori Hideshima¹, Yuya Minoura¹, Akitaka Yoshigoe², Yuden Teraoka², Takuji Hosoi¹, Takayoshi Shimura¹, Heiji Watanabe¹ (Osaka Univ.¹, JAEA²)

Keywords:High-k,Ge,EOT

« Previous in this session
Next in this session »

▲

Presentation information

[17p-B5-1~21] 13.3 Insulator technology

△ [17p-B5-17] High-k/Ge Gate Stack with an EOT of 0.56 nm by Controlling High-k/Ge Interface Reaction Using Ultrathin AlOx Interlayer

△ [17p-B5-17] High-k/Ge Gate Stack with an EOT of 0.56 nm by Controlling High-k/Ge Interface Reaction Using Ultrathin AlO_x Interlayer