The 74th JSAP Autumn Meeting,2013

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Poster presentation

13. Semiconductors A (Silicon) » 13.6 Silicon devices / Integration technology

[18p-P10-1~13] 13.6 Silicon devices / Integration technology

Wed. Sep 18, 2013 1:30 PM - 3:30 PM P10 (Davis Memorial Auditorium)

1:30 PM - 3:30 PM

[18p-P10-7] Gate-first process and EOT-scaling of III-V nanowire-channels on Si

○Katsuhiro Tomioka1,2, Masatoshi Yoshimura1, Takashi Fukui1 (GS-IST, RCIQE, Hokkaido Univ.1, JST-PRESTO2)

Keywords:nanowire,transistor,FET