CMP processes for Si and SiO<sub>2</sub> surfaces using a minimal CMP machine

Norio Umeyama

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Oral presentation

13. Semiconductors A (Silicon) » 13.5 Si process technology

[20a-B4-1~11] 13.5 Si process technology

Fri. Sep 20, 2013 9:00 AM - 12:00 PM B4 (TC2 1F-106)

11:15 AM - 11:30 AM

[20a-B4-9] CMP processes for Si and SiO₂ surfaces using a minimal CMP machine

^○Norio Umeyama^1,2, Fumito Imura^1,2, Katsuhiko Nakato¹, Kazutaka Shibuya^1,3, Yoshio Nakamura^1,3, Kouichiro Ichikawa³, Sommawan Khumpuang^1,2, Shiro Hara^1,2 (MINIMAL¹, AIST², Fujikoshi Machinery³)

Keywords:CMP,ミニマルファブ

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Presentation information

[20a-B4-1~11] 13.5 Si process technology

[20a-B4-9] CMP processes for Si and SiO2 surfaces using a minimal CMP machine

[20a-B4-9] CMP processes for Si and SiO₂ surfaces using a minimal CMP machine