[18p-D8-1~15] 13.2 Insulator technology

[18p-D8-7] Quantitative evaluation of slow traps near Ge MOS interfaces by using time response of MOS capacitance

^○Katsuhisa Tanaka^1,2, Rui Zhang^1,2, Mitsuru Takenaka^1,2, Shinichi Takagi^1,2 (Univ. of Tokyo¹, JST-CREST²)

Keywords:Ge,slow trap