[13a-P14-1~14] 13.4 Si wafer processing /MEMS/Integration technology

[13a-P14-2] Reduction of parasitic resistance in Ge nMOSFETs with metal/n⁺Ge junctions by two-step P-ion implantation

〇Masahiro Koike¹, Yuuichi Kamimuta¹, Kurosawa Etsuo¹, Tsutomu Tezuka¹ (1.GNC, AIST)

Keywords:semiconductor,Ge,contact resistance