The 77th JSAP Autumn Meeting, 2016

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13 Semiconductors » 13.4 Si wafer processing /Si based thin film /MEMS/Integration technology

[15a-B10-1~13] 13.4 Si wafer processing /Si based thin film /MEMS/Integration technology

Thu. Sep 15, 2016 9:00 AM - 12:15 PM B10 (Exhibition Hall)

Wenchang Yeh(Shimane Univ.), Tatsuya Okada(Univ. of the Ryukyus)

10:15 AM - 10:30 AM

△ [15a-B10-6] Performance of an E/D Inverter using Vth Control of Four-Terminal Self-Aligned Planar Metal Double-Gate Low-Temperature Poly-Si TFTs

〇Hiroki Ohsawa1, Akito Hara1 (1.Tohoku Gakuin Univ.)

Keywords:TFT, poly-Si, E/D inverter

We fabricated an E/D inverter using four-terminal self-aligned planar metal double-gate low-temperature poly-Si TFTs. By adjusting the threshold voltages of the TFTs to appropriate values using the control gates, the E/D inverter was driven by 1.0 V drain voltage.