The 77th JSAP Autumn Meeting, 2016

Presentation information

Oral presentation

13 Semiconductors » 13.4 Si wafer processing /Si based thin film /MEMS/Integration technology

[16p-B10-1~12] 13.4 Si wafer processing /Si based thin film /MEMS/Integration technology

Fri. Sep 16, 2016 1:45 PM - 5:00 PM B10 (Exhibition Hall)

Minoru Sasaki(Toyota Tech. Inst.), Kuniyuki Kakushima(Titech)

1:45 PM - 2:00 PM

[16p-B10-1] Development and Characterization of Process Cutting Half-inch Wafers off a Large Wafer

Norio Umeyama1,2, Takaaki Sakai3, Atsushi Kajikura3, Kouichiro Ichikawa3, Sommawan Khumpuang1,2, Shiro Hara1,2 (1.AIST, 2.MINIMAL, 3.Fujikoshi Machinery)

Keywords:minimal, wafer

A method for forming half-inch wafers and its wafer characterization are reported. For the half-inch, the proportion of the wafer edge is large. Since the edge shape affects in a process such as cleaning or resist coating, variously changing the edge shape was optimized. Also not cut out from the small diameter of the crystal, it was developed the process cutting out from a large wafer. We report a cutting process for Si, SOI, GaAs, Ga2O3, and the analysis results of the impurities for the Si wafer.